Advanced digital design with the Verilog HDL /
保存先:
| 第一著者: | |
|---|---|
| フォーマット: | 図書 |
| 言語: | 英語 |
| 出版事項: |
New Delhi :
Prentice Hall,
2005.
|
| 版: | 2nd ed. |
| シリーズ: | Prentice Hall Xilinx design series
|
| 主題: | |
| タグ: |
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MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | 5486 | ||
| 003 | BD-DhMIS | ||
| 005 | 20160313124505.0 | ||
| 008 | 091112s2005 ii a b 001 0 eng | ||
| 020 | |a 8129709368 | ||
| 020 | |a 9788129709363 | ||
| 040 | |a BD-DhMIS |c BD-DhMIS | ||
| 082 | 0 | 0 | |a 621.395 |b CIL |
| 100 | 1 | |a Ciletti, Michael D. | |
| 245 | 1 | 0 | |a Advanced digital design with the Verilog HDL / |c Michael D. Ciletti. |
| 250 | |a 2nd ed. | ||
| 260 | |a New Delhi : |b Prentice Hall, |c 2005. | ||
| 300 | |a 1004 p. : |b ill. ; |c 24 cm. | ||
| 490 | 0 | |a Prentice Hall Xilinx design series | |
| 504 | |a Includes bibliographical references and indexes. | ||
| 650 | 0 | |a Logic design |x Data processing. | |
| 650 | 0 | |a Verilog (Computer hardware description language) | |
| 906 | |a 7 |b cbc |c orignew |d 1 |e ecip |f 20 |g y-gencatlg | ||
| 942 | |2 ddc |c TEXT | ||
| 955 | |b xh12 2009-11-12 |i xh12 2009-11-12 |a xe14 2010-07-21 2 copies rec'd., to CIP ver. | ||
| 999 | |c 5486 |d 5486 | ||